职位描述
Responsibility
1. Design the circuits of IPs used in memory products.
2. Gate-level circuit design of digital blocks, and mix-signal simulation.
3. Simulate, verify and analyze memory functionality and performance.
4. Optimize the circuit timing margin under different PVT conditions.
5. Cooperate with layout engineer for floor plan.
6. Make documents for the block deions, including functions and timing.
7. Cooperate with PE/TE for post silicon results debugging.
Requirement:
1. Good knowledge and deep understanding CMOS circuit design.
2. Familiar with EDA design tools such as spectre, hspice, finesim, Virtuoso etc.
3. Design ability of full-custom combinational logic and sequential logic circuits, able to divide complex circuits into simple logic circuits.
4. Experience in memory design is preferred.
5. Good team player and communication skills.
6. Good learning competency, self-motivated in a flexible and dynami